This invention relates to a vector processor for carrying out vector calculations in accordance with floating-point arithmetic.
A vector processor of the type described, generally has a first and a second processor input bus and a processor output bus. The first and the second processor input buses are supplied with a first and a second input vector, each of which has a plural number of vector components or elements. The vector processor is for calculating a calculation result of a vector calculation in accordance with floating-point arithmetic in response to the first and the second input vectors. The processor output bus is for supplying the calculation result to an external device.
The vector processor comprises a vector calculation unit and a control unit for controlling the vector calculation unit.
The vector calculation unit comprises a pipeline multiplier, a pipeline adder, and first through fourth vector registers. The pipeline multiplier is for calculating a multiplication result of floating-point multiplication in a multiplier pipeline fashion in response to first and second multiplier input operands. The pipeline adder is for calculating an addition result of floating-point addition in a multiplier pipeline fashion in response to first and second adder input operands. For example, such a vector calculation unit is disclosed by Kai Hwang et al in a book "Computer Architecture and Parallel Processing", International student edition, published 1985 by MacGraw-Hill Book Company, pages 264-271, under the heading of "4.4.1 The Architecture of Cray-1".
As will later be described in detail, the pipeline multiplier of the vector calculation unit has a multiplier output terminal connected to a multiplication result bus. The first through the fourth vector registers has register input terminals which are operatively connected to the multiplication result bus through first through fourth selectors, respectively. Likewise, the pipeline adder has an adder output terminal connected to an addition result bus. The register input terminals of the first through the fourth vector registers are operatively connected to the addition result bus through the first through the fourth selectors, respectively. Each of the first through the fourth selectors is furthermore connected to at least one of the first and the second processor input buses and selects one of the multiplication result bus, the addition result bus, and the processor input bus as a selected bus to connect the selected bus to the register input terminal of the vector register in question.
Attention will be directed to a case where the vector calculation unit is implemented by the use of an IC (integrated circuit) or an LSI (large scale integration circuit). Inasmuch as the multiplier output terminal of the pipeline multiplier is operatively connected to all of the first through the fourth vector registers and as the adder output terminal of the pipeline adder is operatively connected to all of the first through the fourth vector registers, connection lines unavoidably occupy a large area on a semiconductor chip in order to operatively connect the multiplier output terminal of the pipeline multiplier to all of the first through the fourth vector registers and to operatively connect the adder output terminal of the pipeline adder to all of the first through the fourth vector registers. This results in a high cost on manufacturing the vector processor.